DTS is looking for a highly skilled and experienced Cadence Allegro Skill and Pads Basic Script Programmer to join our team in Singapore.

Job Description:

Automate the design Process in Cadence Allegro and/or Pads PCB Layout Software by Coding in Skill or Basic Script.

Primary Responsibilities:

• Develop Skill Program in Cadence Allegro or Scripting in Pads layout to automate Placement, Routing and Checks.
• Develop and maintain a database of all useful Skill Programs and/or Scripts to be used across the DTS organization.
• Work closely with PCB Designers on issues and ease their daily working task through automation.
• Work closely with the QC team for checks through automation to ensure Consistent Design Quality.
• Position reports to the DTS Design Manager.

Experience Requirements:

• Minimum of 3 to 5 years in Cadence Allegro Skill Programming or Basic Scripting in Pads Layout is a must.
• Prefer knowledge of both Cadence Allegro Skill and Pads Layout Basic Scripting, and if know only one platform candidate should be willing to learn the other.
• Previous design experience for ATE applications is desired but is not a must.
• Must be highly motivated independent individual who is detailed and team oriented.
• Must be able to multi-task for time critical design schedules.
• Must understand the PCB Layout and Fabrication process and design for manufacturability.

DTS is looking for a highly skilled Senior PCB Designer with SI experience to join our team in Singapore .

Job Description:

Designing Printed Circuit Board layouts for semiconductor test applications utilizing Cadence Allegro Software. Support Signal Integrity and Power Integrity analysis at the PCB board level to meet noise specifications & delivery requirements.

Primary Responsibilities:

• Produce PCB layouts for mixed signal / RF / high-speed designs using Cadence Allegro Software.
• Generate manufacturing files and supporting docs for the designs, including gerber, fab, and assembly drawings.
• Work directly with applications and local engineers to complete all aspects of the ATE PCB development process.
• Power integrity analysis for PCB (e.g. layout extraction, electromagnetic / HSPICE simulation, etc.) to meet specs.
• Optimize layer stack-up & power plane assignment to minimize voltage noise.
• Signal trace length matching and impact to timing.
• Crosstalk analysis and reduction.
• Full-wave simulation and model extraction for signal integrity and power integrity analysis.

Experience Requirements:

• Minimum of 3 to 5 years layout expertise with the Cadence Allegro design platform is a must.
• Solid working knowledge of the constraints manager and design for manufacturability.
• Design experience for ATE applications on Teradyne, Advantest and other platforms is a plus.
• Must possess good electrical knowledge and experience with multilayer high speed, RF and power designs.
• Solid background on transmission line theory and in-depth knowledge of electromagnetics, and PCB layout techniques.
• Experience with SI simulation tools (e.g. Synopsis HSPICE, Ansys HFSS, Q3D, Cadence PowerSI, PowerDC, and Agilent ADS).
• Must understand the PCB fabrication process, and design for manufacturability
• Knowledge on other PCB design software (e.g. Pads / Altium) is a plus

Additional Required Skills:

• Professional attitude and being a team player is a must.
• Well organized with good follow-through skills.
• Good problem solving and debug capabilities.
• Ability to work independently, manage deadlines, and multi-task with minimal direction.
• Excellent communication skills in English required.
• Periodically travel across Asia as required.